A known high-density anti-fuse twin-gate isolation (TGI) OTP memory cell has been realized in a 28 nanometer (nm) high-k metal gate (HKMG) complimentary metal oxide semiconductor (CMOS) logic process to address breakdown between the gate and an n+ doped source/drain (S/D) region as well as program disturb/interference issues due to potential contour distribution. The 28 nm OTP technology addresses the program disturb issue by introducing a p+ implant; however, this results in a larger and less desirable cell size. A 1 kilobit fin-type field effect transistor (FinFET) dielectric (FIND) resistive random-access memory (RRAM) realized in a 16 nm FinFET CMOS logic process or a 16 nm MTP cell is also known. The 16 nm MTP technology has a very low set voltage and reset current due to the field enhancement on fin corners; however, a reduction of the cell size is desirable.
A need therefore exists for methodology enabling formation of a compact OTP/MTP on FDSOI or FinFET architecture that can alleviate program disturb and the resulting devices.